As is well known, static random access memory (SRAM) cells can be implemented using cross-coupled logic gates to maintain logic states corresponding to various associated data values. In this regard, it is generally desirable for SRAM cells to hold their stored logic states despite possible changes in voltage, temperature, or other operating conditions. It is also desirable for SRAM cells to permit changes in their logic states in response to write operations. Unfortunately, existing SRAM cell designs often fail to provide high degrees of both stability and writeability.
For example, in one approach to improve stability and writeability, the minimum and maximum operating voltage of an SRAM cell may be limited. However, such implementations can become impractical due to possible changes in voltage caused by environmental or other operating conditions.
In an approach to improve stability, an SRAM cell may be implemented with robust cross-coupled logic gates that are resilient to outside disturbances. However, if the SRAM cell is too robust, it can become difficult for the SRAM cell to switch to a newly written logic state. For example, if the SRAM cell's PMOS transistors are too strong, they may prevent one of the SRAM cell's internal nodes from being pulled down to an appropriate voltage corresponding to a newly written logic state. This can negatively affect the writeability of the SRAM cell.
In an approach to improve writeability, the cross-coupled logic gates of an SRAM cell may be weakened. Nevertheless, the logic states stored by the weakened SRAM cell may inadvertently change in response to variations in operating conditions, thereby compromising stability. Such a weakened SRAM cell can also impair writeability if the SRAM cell is unable to regenerate newly written logic states between its cross-coupled logic gates. For example, if the SRAM cell's PMOS transistors are too weak, they may be unable to pull up one of the SRAM cell's internal nodes to an appropriate voltage in response to a newly written logic state.
In another approach to improve writeability, a single power switch may be connected with a column of SRAM cells to reduce the voltage provided to all cross-coupled portions of the SRAM cells during write operations in response to write enable and column select signals. Although this approach may permit the voltage of one node of an SRAM cell to be easily pulled down, the reduced voltage on both cross-coupled logic gates can inhibit the SRAM cell's ability to adequately pull up the voltage of a second node of the SRAM cell in order to regenerate the newly written logic state between its cross-coupled logic gates.
Other efforts to improve writeability, such as increasing the size or strength of external circuit elements connected to word lines, lowering threshold voltages of transistors of the SRAM cell, increasing the word line voltage, or weakening the access transistors connected to the word lines can also negatively impact stability. Moreover, as SRAM operating voltages are reduced, variations in operating conditions and SRAM components can more easily impact the operation of SRAM cells which can have a correspondingly greater effect on stability and writeability.